The present invention relates generally to MOS-gated devices, and more specifically to MOS-gated device fabrication techniques and structures.
Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) are a type of transistor having a layer of dielectric between a conductive gate and a semiconductor region. MOSFETs may be designed to operate in enhancement mode or depletion mode. Enhancement mode MOSFETs operate by creating a conductive channel through inversion of the semiconductor surface underneath the gate, that is, by applying a voltage to the gate electrode and creating a region in the semiconductor where the concentration of xe2x80x9cminorityxe2x80x9d carriers (holes in the case of n-type semiconductors, and conduction electrons in the case of p-type semiconductors) is increased until it exceeds the equilibrium concentration of xe2x80x9cmajorityxe2x80x9d carriers (by contrast, a depletion mode device operates by applying a voltage to a gate, and reducing the number of carriers to a value lower than the equilibrium value in an already present conductive channel). The conductive channel so created typically extends laterally or vertically between the source and the drain of the device.
Power MOSFETs are a type of MOSFET designed to handle high voltages and/or high currents. In one type of power MOSFETxe2x80x94a double diffused MOSFET (DMOS)xe2x80x94the body and source regions are diffused from the same edge. DMOS devices may be either lateral or vertical devices, depending on whether the current flow between the source and drain is lateral or vertical, respectively. Vertical DMOS technology is used to fabricate a variety of device types, including high voltage and high current transistors and IGBTs (Insulated Gate Bipolar Transistors). The large majority of these vertical DMOS devices are n-channel rather than p-channel devices, due to the lower on-resistance or voltage drop per unit area afforded by n-channel devices as compared to p-channel devices. This lower on-resistance or voltage drop per unit area is a result of the higher mobility of conduction electrons in silicon compared to that of holes.
As with other MOSFETs, vertical DMOS devices may he enhancement mode or depletion mode devices. In an n-channel enhancement mode device, the threshold voltage of the devicexe2x80x94that is, the voltage required to be applied to the gate in order to create a conductive channel between the source and the drain, which is also the voltage necessary to effect inversionxe2x80x94is typically chosen to be sufficiently positive with respect to the source voltage to allow the device to be fully xe2x80x9coffxe2x80x9d with 0 volts present between the gate and the source. In an n-channel depletion mode device, by contrast, the threshold voltage is typically chosen to be sufficiently negative with respect to the source voltage to allow the device to be fully xe2x80x9conxe2x80x9d with 0 volts present between the gate and the source. In depletion mode n-channel devices, the conductive channel in the device is typically formed either by introducing n-type dopant at the surface of the body region which produces a permanent channel region with no gate-to-source voltage, or by implanting permanently charged ions into the gate dielectric which induce a channel at the surface of the underlying body region when there is no gate-to-source voltage.
A conventional vertical DMOS is illustrated in FIG. 1. Devices of this type are described, for example, in R. Locher, xe2x80x9cIntroduction to Power MOSFETS and Their Applicationsxe2x80x9d, National Semiconductor Application Note 558 (December 1988). The device 1 consists of an n+ substrate 2, on one surface of which is disposed an epitaxial layer 3 and on the other surface of which is disposed a metal layer 5 which serves as a drain contact having a drain terminal 6. A deep body region 7 is in electrical contact with a source and body terminal 4 and is formed in the epitaxial layer. In the device illustrated, the shallower diffused region 10 is a p body region and the deeper diffused region is a p+ body region. A portion 13 of the p body region extends underneath the gate between the n+ source region 9 and the drain region 21 and is capable of undergoing inversion to form a channel.
A conductive polysilicon gate 15 is disposed over the channel. The gate is surrounded by a dielectric material 17 (typically SiO2). The portion of this dielectric material below the gate is referred to as the gate dielectric. A layer of source and body metal 19 is disposed over the gate and the epitaxial layer, but in contact with just the source and body regions.
When the gate is biased positive with respect to the source and there is an applied drain-to-source voltage, the holes in the p-type body region 13 are repelled away from the gate area and conduction electrons are drawn towards it, thus inverting the p-type body regions underneath the gate. This gate-to-source voltage creates a path or channel so that carriers from the source can flow to the drain region at the surface below the gate, and then vertically through drain region 21, and to the n+ substrate 2. The vertical geometry of these devices allows lower on-state resistances for the same blocking voltage and faster switching than is possible in comparable lateral MOSFETS.
The threshold voltage of both enhancement mode and depletion mode DMOS devices varies from one device to another. The degree of threshold voltage variation across a group of devices is determined by a variety of manufacturing variables, including the exact doping profile in the body region, the gate dielectric thickness and composition, and the composition of the gate conductor. In typical switching applications, variations in the manufacturing threshold voltage do not present a problem with respect to enhancement mode DMOS devices, because the drive signal is chosen to turn the device fully xe2x80x9conxe2x80x9d or fully xe2x80x9coffxe2x80x9d. However, while depletion mode DMOS devices may be employed in a similar manner, the current verses voltage characteristics of depletion mode DMOS devices (see FIG. 2) for an n-channel DMOS transistor also allows them to be used in a two terminal configuration in applications that require a specific current with zero volts between the gate and the source. Only two terminals are required in such a configuration, because the gate is electrically connected to the source. Some of these applications are described, for example, in S. Ochi, xe2x80x9cSemiconductor Current Regulators Protect Circuitsxe2x80x9d, PCIM, Vol. 26, No. 1, p.63 (January 2000). In many of these applications, the ability to provide a specific current (within the limits of design specifications) is essential to their use. However, due to the above noted variations in threshold voltages of DMOS devices, the current that flows with zero volts between the gate and source may vary significantly) even among devices manufactured using the same process flow.
There is thus a need in the art for depletion mode MOS-gated devices having a threshold voltage that may be adjusted so as to provide a desired current flow with zero volts between the gate and the source. There is also a need in the art for methods for making such devices and for adjusting the threshold voltages thereof These and other needs are met by the present invention, as hereinafter described.
In a first aspect, the present invention relates to a transistor comprising a floating gate, a programming electrode, a dielectric material, a source, a body and a source/body metallization layer which is in electrical contact with the source and body, and also serves as a gate of the device. The source/body contact and gate metal layer serves as a reference voltage for the floating gate. The threshold voltage of the transistor is adjustable from an initial voltage V0 to a new voltage Vn, wherein |V0xe2x88x92Vn| greater than 0 and Vn less than 0 (in an n-channel device) by causing electrons to tunnel through a dielectric material so as to change the net electric charge on the floating gate. Preferably, |Vn| is at least 0.1 volts, and more preferably is within the range of about 1.0 to about 10.0 volts. The transistor is preferably a MOSFET, and more preferably a lateral or vertical power MOSFET. In the preferred embodiment, the dielectric material, which may be, for example, an oxide layer, a nitride layer, or a composite dielectric layer, is disposed between the floating gate and one of the programming electrodes, and is sufficiently thin (e.g., less than about 250 xc3x85, and more preferably within the range of about 50 to about 250 xc3x85) to allow Fowler-Nordheim tunneling or other types of field assisted electron tunneling between the floating gate and this programming electrode. The source employed in an n-channel transistor is preferably an n+ source. The transistor also preferably comprises double diffused source and body regions.
A second aspect of this invention differs from the first aspect only in that the metallization layer which is in electrical contact with the source and body does not also serve as the gate of the device. The gate is a separate region that can be independently biased with respect to the source and body.
In certain variations of the above noted aspects of the present invention, the thin dielectric layer where tunneling occurs can be disposed between the source/body metallization layer and the floating gate, between the floating gate and a separate poly programming layer, between either an n-doped or a p-doped region of silicon and the floating gate, or between the device gate and the floating gate. In all instances there is both a top and bottom programming electrode. In these variations, tunneling is made to occur either between the floating gate and the top programming electrode or between the floating gate and the bottom programming electrode. The programming electrodes are each separated from the floating gate by a dielectric layer. The programming electrode that carriers tunnel to and from is separated from the floating gate by a dielectric layer that is thinner than the dielectric layer separating the floating gate from the other programming electrode.
In another aspect, the present invention relates to a method for adjusting the threshold voltage of a MOS-gated device. In accordance with the method, a MOS-gated device is provided which comprises a floating gate, programming electrodes, dielectric materials, a source and drain, and a source/body metallization layer in electrical contact with the source and body which also serves as a gate for the device. The source/body and gate metal preferably also serves as a reference voltage for the floating gate. The MOS-gated device may be of the type described in the above noted aspects of the present invention. The threshold voltage of the transistor is then adjusted from an initial voltage V0 to a new voltage Vn, wherein |V0xe2x88x92Vn| greater than 0, by causing electrons to tunnel through a dielectric material so as to change the net electric charge on the floating gate. This floating gate adjusts the threshold voltage of the device with respect to the reference gate.
In yet another aspect, the present invention relates to a method for adjusting the threshold voltage of a MOS-gated device. In accordance with the method, a MOS-gated device is provided which comprises a floating gate, programming electrodes, dielectric materials, a source and drain, a source/body metallization layer and a gate that is biased with respect to the source/body metallization. The MOS-gated device may be of the type described in the above noted aspects of the present invention. The threshold voltage of the transistor is then adjusted from an initial value V0 to a new voltage Vn, wherein |V0xe2x88x92Vn| greater than 0, by causing electrons to tunnel through a dielectric material so as to change the net electric charge on the floating gate. This floating gate adjusts the threshold voltage of the device with respect to the gate.
In still another aspect, a DMOS current source is provided which comprises first and second programming electrodes, a floating gate disposed between the first and second programming electrodes, and a dielectric material disposed between the floating gate and at least one of said first and second programming electrodes. She threshold voltage of the DMOS current source is adjustable from an initial voltage V0 to a new voltage Vn by applying a voltage between said first and second programming electrodes sufficient to cause charged carriers to tunnel through the dielectric material so as to change the net electric charge on said floating gate, and wherein |V0xe2x88x92Vn| greater than 0.
In yet another aspect, a MOSFET is provided which comprises first and second electrodes, a floating gate disposed between the first and second electrodes, and a dielectric material disposed between the floating gate and the first electrode. The thickness of the dielectric material disposed between the floating gate and the first electrode is within the range of about 50 xc3x85 to about 250 xc3x85, and preferably within the range of about 80 xc3x85 to about 200 xc3x85.
In another aspect, a MOSFET is provided which comprises first and second electrodes, a floating gate disposed between the first and second electrodes, and a dielectric material disposed between the floating gate and the first electrode. The threshold voltage of the MOS-gated device is adjustable by applying a sufficient voltage across said first and second electrodes.
These and other aspects of the present invention are described in further detail below, and with frequent reference to an n-channel DMOS device as an example.